Any switched-capacitor (SC) converter, regardless of its topology or conversion ratio, can be modeled from a black-box perspective by its Thévenin equivalent. This simplifies the converter to an ideal DC-DC transformer with a conversion ratio $M$, an ideal voltage source $V_{out, ideal} = M \times V_{in}$, and a single equivalent output resistance, $R_{out}$. This resistance isn't a physical resistor but an abstraction that models all power loss mechanisms within the converter, including both conduction and charge-transfer losses. Understanding $R_{out}$ is the key to analyzing and optimizing converter performance.

The value of $R_{out}$ is highly dependent on the switching frequency, $f_{sw}$. Its behavior is best understood by examining two asymptotic operational regimes: the Slow Switching Limit (SSL) and the Fast Switching Limit (FSL).

In the Slow Switching Limit (SSL), the switching period ($T_{sw} = 1/f_{sw}$) is much longer than the RC time constants of the charge transfer paths. This condition ensures that during each switching phase, the flying capacitors have sufficient time to fully charge or discharge, reaching equilibrium with the source or load. The dominant loss mechanism here is not conduction but the inherent energy dissipation from charge redistribution. When a capacitor at one voltage is connected to a node at another, charge flows until the voltages equalize, and this process inherently loses energy. Because the total charge transferred per cycle is fixed for a given load current, the power loss becomes proportional to the frequency at which this transfer occurs. Consequently, the equivalent resistance in the SSL is inversely proportional to the switching frequency.

Conversely, in the Fast Switching Limit (FSL), the switching period is much shorter than the circuit's RC time constants. The capacitors no longer fully charge or discharge in each phase. Instead, they experience only a small voltage ripple as they shuttle charge. In this regime, the charge redistribution losses that defined the SSL become negligible. The dominant loss mechanism shifts to pure conduction losses through the resistive elements of the circuit, primarily the on-resistance of the switches ($R_{on}$) and the equivalent series resistance (ESR) of the capacitors. Since these are physical resistances, the resulting equivalent output resistance, $R_{FSL}$, is independent of the switching frequency.

A real SC converter operates across a spectrum of frequencies, transitioning between these two ideal limits. To create a unified model for $R_{out}$ that is valid at any frequency, we need a method to interpolate between $R_{SSL}$ and $R_{FSL}$. The losses from these two limits are largely orthogonal, representing distinct physical phenomena (charge sharing vs. conduction). Therefore, they can be combined in a manner analogous to adding orthogonal vectors.

A widely used and effective method is the Minkowski distance approximation, which uses a square-root of the sum of squares (SRSS) approach. This provides a smooth and accurate transition between the two asymptotic lines.

This combined model reveals a critical trade-off in SC converter design. At low frequencies, performance is limited by charge-transfer losses, and increasing the switching frequency yields significant reductions in output impedance. However, beyond a certain point—the 'knee' of the curve where $R_{SSL} \thickapprox R_{FSL}$—the benefits diminish rapidly. At very high frequencies, the impedance flattens out, limited only by the parasitic resistances of the components. Pushing the frequency higher in this FSL region provides no improvement in efficiency and may even degrade it due to increased gate drive losses.

The power of this unified model is its ability to predict converter performance and guide design choices, such as selecting the optimal switching frequency that balances efficiency and component size.